Architektura układów FPGA cz.2
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Architektura układów FPGA cz.2
Module: Electronics & Telecomunication, 5rd year Programmable Logical Devices FPGA architectures Part 2 J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH 1 Agenda • FPGA market offer • Altera (Intel) • Lattice • Actel (Microsemi) • Cypress • FPGA startups • Achronix • Tabula • SoC – FPGA + uP • NIOS (Altera) • PicoBlaze, MicroBlaze (Xilinx) • ARM ( all ☺) J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH References WWW FPGA manufactures • Big labels ( in alphabetical order) – – – – • FPGA startups – – • http://www.achronix.com http://www.tabula.com general – – • www.actel.com (Microsemi) www.altera.com www.cypress.com www.latticesemi.com http://www.soccentral.com www.eetimes.com/design/programmable-logic King of the kings ☺ embedded: – www.arm.com J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera – top FPGA offer J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera FPGA series Cyclone V J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera FPGA series Cyclone V ■ Technology: ■ 28-nm TSMC low-power process technology ■ 1.1-V core voltage ■ Low-power serial transceivers: ■ 614 Mbps to 5.0 Gbps integrated transceivers ■ Transmit pre-emphasis and receiver equalization ■ Dynamic partial reconfiguration of individual channels ■ General purpose I/Os (GPIOs): ■ 875 Mbps LVDS (receiver), 840 Mbps LVDS (transmitter) ■ 400 MHz/800 Mbps external memory interface ■ On-chip termination (OCT) ■ 3.3-V support with up to 16 mA drive strength ■ Embedded transceiver I/O hard IP: ■ Basic mode (up to 5.0 Gbps) ■ PCIe Gen2 x1, x2 and Gen1 x1, x2, or x4; with multi-function, endpoint, and root port ■ Gigabit Ethernet (GbE) and XAUI PCS ■ Serial RapidIO® (SRIO) PCS ■ Common Public Radio Interface (CPRI) PCS ■ JESD204A PCS ■ OBSAI PCS ■ SATA PCS ■ SDI SD/HD and 3G-SDI PCS ■ DisplayPort PCS ■ Vx1 PCS ■ High-performance core fabric: ■ Enhanced 8-input ALM with four registers J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera FPGA series Cyclone V Variable precision DSP blocks hard IP: ■ Natively support three signal processing precision ranging from three 9 × 9s, two 18 × 19s, or one 27 × 27 in the same variable precision DSP block ■ 64-bit accumulator and cascade ■ Embedded internal coefficient memory ■ Pre-adder/subtractor improves efficiency ■ Internal memory blocks: ■ M10K, 10-Kbit with soft error correction code (ECC) ■ Memory logic array block (MLAB), 640-bit distributed LUTRAM—up to 25% of the ALMs can be used as MLAB memory ■ DDR3, DDR2, LPDDR, and LPDDR2 memory controller hard IP ■ Partial and dynamic reconfiguration of the FPGA ■ PLLs: ■ Precision clock synthesis, clock delay compensation, and zero delay buffering ■ Integer mode and fractional mode ■ Clock networks: ■ 625 MHz global clock network ■ Global, quadrant, and peripheral clock networks ■ Unused clock networks can be powered down to reduce dynamic power ■ Configuration: ■ Configuration via Protocol (CvP) ■ Active Serial (x1 and x4), Fast Passive Parallel (x8 and x16), Passive Serial, and JTAG options ■ Enhanced advanced encryption standard (AES) design security features ■ Tamper protection ■ Packaging: ■ Wirebond halogen-free packages ■ Multiple device densities with compatible package footprints for seamless migration between different device densities ■ Lead and RoHS-compliant options J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera FPGA series Aria 10 J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera FPGA series Aria 10 The Arria® 10 device family includes three variants: • Arria 10 GT FPGAs: Up to 96 full-duplex optimized transceivers with data rates up to 28.1 Gbps chip-to-chip, and up to 1150K equivalent Logic Elements (LEs) • Arria 10 GX FPGAs: Up to 96 full-duplex transceivers with data rates up to 17.4 Gbps chip-to-chip, 16.0 Gbps backplane, and up to 1150K equivalent LEs • Arria 10 SX SoCs: Integrated ARM® CortexTM -A9 hard processor systems (HPS) with up to 48 full-duplex transceivers with data rates up to 17.4 Gbps chip-to-chip, 16.0 Gbps backplane, and up to 660K equivalent LEs J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera FPGA series Aria 10 Transceivers J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera FPGA series Aria 10 J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera FPGA series Aria 10 J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera FPGA series Aria 10 J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera FPGA series Aria 10 J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera FPGA series Aria 10 J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera FPGA series Aria 10 SoC J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera FPGA series Stratix 10 J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera FPGA series Stratix 10 Stratix 10 GT FPGAs For the most demanding applications requiring ultra-high bandwidth and performance Stratix 10 GT FPGA transceivers support data rates up to 56 Gbps Stratix 10 GX FPGAs Built for high performance and bandwidth applications such as multi-100G/400G systems Stratix 10 GX FPGA transceivers support 32 Gbps chip-module, chip-to-chip, and backplane operations at up to 28 Gbps Built for high performance and power-efficient computing applications such as data center acceleration, radar, and line card processing Stratix 10 SX SoCs Built for maximum processor performance per watt for highbandwidth applications with an integrated HPS Stratix 10 SX SoCs feature hard processor system with 64 bit quad-core ARM Cortex-A53 processor - See more at: http://www.altera.com/devices/fpga/stratixfpgas/stratix10/stx10-index.jsp J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera FPGA series Stratix 10 Industry’s First Gigahertz FPGAs and SoCs •New ultra-high performance FPGA architecture •2x the core performance of prior generation high-end FPGAs •>10 TFLOPs of single-precision floating-point DSP performance •>4x processor data throughput of prior-generation SoCs Break the Bandwidth Barrier with Unimaginable High-Speed Interface Rates •4x serial transceiver bandwidth from previous generation FPGAs for high port count designs •28 Gbps backplane capability for versatile data switching applications •56 Gbps chip-to-chip/module capability for leading edge interface standards •Over 2.5 Tbps bandwidth for serial memory with support for Hybrid Memory Cube •Over 1.3 Tbps bandwidth for parallel memory interfaces with support for DDR4 at 3200 Mbps J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera FPGA series HardCopy V J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH FPGA from Lattice This is not to say that Lattice doesn’t innovate. They do. In fact, Lattice basically created the “mid-range” FPGA category that both Xilinx and Altera have now adopted. When Lattice rolled out the first low-cost FPGA with high-speed serial interfaces, they sent their larger competitors into a spin, trying to rapidly re-define the line between their expensive, high-end FPGAs with SerDes and their marketsaturating low-cost FPGAs with conventional IO. Lattice has consistently looked at profitable market segments, designed better mouse traps specifically for those segments, and quietly raised victory flags over numerous applications in whose small ponds they had suddenly become the big fish. J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH FPGA from Lattice J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Flagship FPGA from Lattice iCE40 Lattice acquired iCE40 from Silicon Blue J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Lattice iCE40 – very small packages available J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Lattice FPGA applications J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH FPGA from Actel (Microsemi) J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH FPGA from Actel (Microsemi) J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH FPGA from Actel (Microsemi) J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Actel – mixed signal FPGA J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Actel – mixed signal FPGA J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Actel – „antifuse” technology J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Actel – „antifuse” technology J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Actel – „antifuse” technology J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Cypress PSoC Programmable System-on-Chip J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Cypress PSoC Programmable System-on-Chip J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH The fastest FPGA? Achronix? J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH The fastest FPGA? Achronix J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH picoPIPE Achronix An important concept to highlight is the 'Data Token'. In conventional logic, a Data Token is a logic value at a clock edge. With traditional logic implementations, data is always present, but is only valid (and therefore propagated) when a clock edge is received at a storage element. Hence every time data is propagated from one storage element to the next, only a distinct, valid data value or 'Data Token' is propagated. picoPIPE stages are the atomic elements of the Achronix FPGA fabric. The fabric is capable of implementing any logic function. To implement a logic function, picoPIPEs use explicit Data Tokens, rather than propagating data in response to a global clock edge. A Data Token in picoPIPE logic can be considered as the data and the clock edge merged together. The keyinnovation that enables the picoPIPE fabric to operate at high frequency is this new representation of Data Tokens. J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH The fastest FPGA? Tabula Spacetime? J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Tabula Spacetime Programmable logic company Tabula is rumored to close its doors on March 24 2015 J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH FPGA SoC (marketing data from Altera) J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Softprocessor for FPGA J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera FPGA SoC J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera Softprocessor NIOS II J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera Softprocessor NIOS II J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera Softprocessor NIOS II J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera Softprocessor NIOS II J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera Softprocessor NIOS II J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera Softprocessor NIOS II J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera Softprocessor NIOS II J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera Softprocessor NIOS II J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera Softprocessor NIOS II J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera Softprocessor NIOS II J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Why ARM ?? J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Why ARM ?? ~2011 ~ 200pcs/sec J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Why ARM ?? J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Why ARM ?? J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Altera ARM based SoC SoC FPGAs integrate an ARM-based hard processor system (HPS) consisting of processor, peripherals, and memory interfaces with the FPGA fabric using a highbandwidth interconnect backbone. The Arria® V SoC FPGAs reduce system power, system cost, and board size while increasing system performance by integrating discrete processor, FPGA, and digital signal processing (DSP) functions into a single, user customizable ARM-based system on a chip (SoC). SoC FPGAs provide the ultimate combination of hardened intellectual property (IP) for performance and power savings, with the flexibility of programmable logic J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Xilinx PicoBlaze softprocessor PicoBlaze microcontroller supports the following features: • 16 byte-wide general-purpose data registers • 1K instructions of programmable on-chip program store, automatically loaded during FPGA configuration • Byte-wide Arithmetic Logic Unit (ALU) with CARRY and ZERO indicator flags • 64-byte internal scratchpad RAM • 256 input and 256 output ports for easy expansion and enhancement • Automatic 31-location CALL/RETURN stack • Predictable performance, always two clock cycles per instruction, up to 200 MHz or 100 MIPS in a Virtex-II Pro FPGA • Fast interrupt response; worst-case 5 clock cycles • Optimized for Xilinx Spartan-3 architecture —just 96 slices and 0.5 to 1 block RAM • Support in Spartan-6, and Virtex-6,7 FPGA architectures • Assembler, instruction-set simulator support J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH IDE for PicoBlaze (Mediatronix) no direct support - webpage closed J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH MicroBlaze J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH MicroBlaze J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH MicroBlaze J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Xilinx Zynq-7000 Extensible Processing Platform J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Xilinx Zynq-7000 Virtual Platform A virtual platform enables the development, integration and test of full software stacks without access to real hardware. Virtual platforms also provide new capabilities that can significantly reduce development time compared to traditional hardware-based approaches. Xilinx provides multiple virtual platform choices to address the cost, capability and extensibility needs of different developers. Each virtual platform can be described as a functional simulator which includes a fast instruction set simulator for the ARM® Cortex™ A9 MPCore™ processor, models of the Zynq™-7000 EPP peripheral set, memory, and ancillary peripherals necessary to create a full development platform. Every device model is register-accurate, ensuring that they will run the same production binaries as the actual hardware. J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH Thank you ! J.Kasperek & P.J.Rajda © 2015 Katedra Elektroniki AGH 66