AD670 - Zakład Pomiarów i Systemów Sterowania

Transkrypt

POLITECHNIKA ŚLĄSKA
INSTYTUT AUTOMATYKI
ZAKŁAD SYSTEMÓW POMIAROWYCH
Gliwice, wrzesień 2007
Badanie charakterystyk przetworników c/a i a/c
Cel ćwiczenia
Celem ćwiczenia jest zapoznanie z budową, zasadą działania oraz charakterystykami
dokładnościowymi przetwornika cyfrowo-analogowego z drabinką rezystancyjną R-2R typu
AD7224KN firmy Analog Devices oraz przetwornika analogowo-cyfrowego z kompensacją
wagową typu AD670J firmy Analog Devices.
Zadania
Część I: Badanie przetwornika c/a
1. Umieścić w protokole dane badanego przetwornika c/a.
2. Po zapoznaniu się ze stanowiskiem zaproponować procedury wyznaczania:
a. błędu zera i skalowania,
b. błędów nieliniowości całkowej i różniczkowej,
c. własności dynamicznych przetworników c/a.
3. Ustawić napięcie zasilające przetworniki na 15V, a napięcie odniesienia na 10,24 V.
Obliczyć nominalną wartość kwantu oraz nominalne napięcie maksymalne
przetwornika dla takich nastaw.
4. Wyznaczyć błędy zera i wzmocnienia (skalowania) badanych przetworników.
5. Dla jednego przetwornika wykonać pomiary pozwalające wyznaczyć błędy
nieliniowości całkowej i różniczkowej. Zbadać trzy fragmenty charakterystyki
przetwornika: na początku, na końcu i w środku zakresu przetwornika, każdy
fragment o długości 8 słów kodowych. Obliczyć wartości błędów nieliniowości
różniczkowej i całkowej dla zbadanych fragmentów charakterystyki. Podać
maksymalne wartości tych błędów i porównać je z dopuszczalnymi wartościami
deklarowanymi przez producenta. Sporządzić wykresy błędów nieliniowości
różniczkowej i całkowej.
6. Dla wybranego przetwornika zmierzyć własności dynamiczne, wykorzystując
oscyloskop na stanowisku oraz generator wewnętrzny testera przetworników c/a.
Zmierzyć czas ustalania i szybkość ustalania odpowiedzi. Obserwowany przebieg
przerysować do protokołu.
Część I: Badanie przetwornika a/c
1. Przetwornik a/c pracuje w konfiguracji unipolarnej przy nominalnym zakresie
przetwarzania 2,55 V.
a. obliczyć maksymalną częstotliwość próbkowania przetwornika,
b. obliczyć maksymalną wartość słowa kodowego przetwornika w notacji
dziesiętnej,
c. obliczyć wartość kwantu nominalnego przetwornika oraz nominalne wartości
napięć wejściowych przetwornika, przy których następuje przeskok słowa
kodowego z 0d na 1d oraz z przedostatniego na ostatni.
2. Zmierzyć wartości napięć wejściowych przetwornika, przy których następuje
przeskok słowa kodowego z 0d na 1d oraz z przedostatniego na ostatni. Obliczyć
rzeczywistą wartość kwantu przetwornika oraz błędy zera i wzmocnienia
przetwornika.
3. Zmierzyć wartości napięć wejściowych przetwornika, przy których następuje
przeskok słowa kodowego. Zbadać trzy fragmenty charakterystyki przetwornika: na
początku, na końcu i w środku zakresu przetwornika, każdy fragment o długości 8
przeskoków. Obliczyć wartości błędów nieliniowości różniczkowej i całkowej dla
zbadanych fragmentów charakterystyki. Podać maksymalne wartości tych błędów i
porównać jez dopuszczalnymi wartościami deklarowanymi przez producenta.
Sporządzić wykresy błędów nieliniowości różniczkowej i całkowej.
4. Zmierzyć zakres wartości napięć wejściowych przetwornika, przy których wartość
słowa kodowego jest nieustalona (występują przeskoki słowa kodowego). Pomiary
wykonać dla trzech słów kodowych na początku, na końcu i w środku zakresu
przetwornika.
5. Obserwować na oscyloskopie przebieg napięcia na wyjściu status przetwornika.
Wyznaczyć czas przetwarzania przetwornika oraz częstotliwość próbkowania.
Narysować obserwowany przebieg.
Zadania do opracowania sprawozdania
W sprawozdaniu należy wyznaczyć wartości liczbowe wszystkich parametrów
przetworników c/a i a/c badanych podczas ćwiczenia i uzupełnić tabelę z danymi producenta
o uzyskane wyniki. Dokonać opisowego podsumowania wyników badań poprzez porównanie
uzyskanych danych z danymi producenta. Dodatkowo umieścić w sprawozdaniu
w adekwatnym miejscu wykresy przebiegów błędów nieliniowości całkowej i różniczkowej
badanych przetworników.
Pytania kontrolne
1.
2.
3.
4.
5.
6.
7.
8.
9.
Jaka jest budowa typowego przetwornika c/a?
Wymienić podstawowe parametry statyczne przetwornika c/a.
Wymienić podstawowe parametry dynamiczne przetwornika c/a.
Jak wyznaczyć błąd skalowania przetwornika c/a?
Jak definiuje się błędy nieliniowości przetwornika c/a?
Jak wyznaczyć błąd nieliniowości całkowej przetwornika c/a?
Jak wyznaczyć błąd nieliniowości różniczkowej przetwornika c/a?
Jak wyznaczyć (oszacować) czas ustalania badanego przetwornika c/a?
Gdzie stosuje się przetworniki c/a?
1. Opisać zasadę działania przetwornika a/c z kompensacją wagową. Narysować
przebiegi napięcia mierzonego i wzorcowego w funkcji czasu dla pełnego cyklu
przetwarzania. Jaki wpływ ma zmiana rozdzielczości przetwornika na jego czas
przetwarzania.
2. Narysować charakterystykę idealną i rzeczywistą 2-bitowego przetwornika a/c. Na
narysowanej charakterystyce wskazać i zdefiniować następujące pojęcia: nominalny
zakres napięcia wejściowego, kwant i błąd kwantyzacji przetwornika, błędy zera
i wzmocnienia, błędy liniowości różniczkowej i całkowej.
3. Opisać, na czym polega różnica pomiędzy konfiguracją unipolarną i bipolarną
przetwornika. Narysować charakterystykę przetwarzania przetwornika w konfiguracji
bipolarnej zgodnie ze wskazówkami producenta (zwrócić uwagę na sposób kalibracji
przetwornika dla konfiguracji bipolarnej)
Literatura
1. Piotrowski J.: Podstawy miernictwa, WNT, Warszawa, 2002.
2. Marcyniuk A.: Podstawy miernictwa elektrycznego, skrypt Pol. Śl., Wyd. Pol. Śl.,
Gliwice 2000
Informacje uzupełniające
Opis stanowiska
Na stanowisku znajduje się tester przetworników analogowo-cyfrowych, woltomierz cyfrowy,
oscyloskop oraz termostat powietrzny.
Tester przeznaczony jest do równoczesnego badania czterech przetworników c/a. Montuje się je w
oprawkach umieszczonych w gniazdach na tylnej ściance obudowy. Każdy z przetworników posiada oddzielną
regulację napięcia odniesienia i korekcji zera, oraz wspólną regulację napięcia zasilania. Kod wejściowy może
być ustawiany albo za pomocą przełączników kodowania przetworników, albo przez gniazdo sterowania
zdalnego. Wbudowany generator przebiegu prostokątnego umożliwia badanie parametrów dynamicznych.
Wtedy to na wejście przetwornika naprzemiennie jest podawane słowo ustawione przełącznikami kodowania
i słowo 0000 0000b. W razie konieczności istnieje możliwość podłączenia zewnętrznego generatora przebiegu
prostokątnego.
Gniazda umieszczone na przedniej ściance obudowy umożliwiają pomiar wszystkich napięć
wejściowych i wyjściowych przetworników. Dodatkowe gniazdo wspólne zapewnia pomiar dowolnego z napięć
bez konieczności przełączania przewodów pomiarowych.
WYŁĄCZNIK
ZASILANIA
Zasilanie
GENERATOR
Przetwornik 1
BLOKI
PRZETWORNIKÓW 1÷4
Przetwornik 2
SYGNALIZACJA
REJESTRÓW
Przetwornik 3
Przetwornik 4
CS
zał
wył
Generator
Uodn
Uwy
Uzera
zał
Uodn
Uwy
Uzera
zał
Uwy
Uzera
zał
Uzera
Uodn
zał
Uzera
wył
WR
Uwy
Uzera
zał
Uzera
wył
wył
Uodn
LDAC
Uzera
wył
RESET
wył
zew
1
Uzas
Przetwornik
ZASILANIE
PRZETWORNIKÓW
Uwy
2
wew
Zdalne
sterowanie
rejestrami
Uodn
3
Uzera Gniazdo
4
Uzas
wspólne
27
26
25
24
23
22
21
20
Zdalne
kodowanie
przetworników
Parametr
RESET
przetworników
GNIAZDO
WSPÓLNE
KODOWANIE
PRZETWORNIKÓW
STEROWANIE
REJESTRAMI
Podstawowe definicje parametrów przetwornika c/a
Błąd zera – różnica pomiędzy zmierzoną wartością napięcia wyjściowego dla słowa 0000 0000b a
wartością teoretyczną.
Błąd czułości (skalowania, wzmocnienia) – różnica pomiędzy zmierzoną wartością napięcia
wyjściowego, pomniejszonego o błąd zera, dla największego słowa kodowego (1111 1111b), a wartością
teoretyczną UMAX.
Błędy nieliniowości wyznacza się po skorygowaniu błędu zera i wzmocnienia.
Nieliniowość różniczkowa – różnica pomiędzy rzeczywistą wartością kwantu a skorygowaną wartością
kwantu. Rzeczywista wartość kwantu to różnica pomiędzy dwoma napięciami wyjściowymi dla kolejnych słów
kodowych (np. U0001 0000b-U0000 1111b). Skorygowana wartość kwantu to wartość obliczona poprzez podzielenie
zakresu przetwarzania przez największą wartość słowa kodowego (tj.
U 255d − U 0d
). Jako błąd nieliniowości
255
różniczkowej podaje się największą wyznaczoną nieliniowość różniczkową.
Nieliniowość całkowa – różnica pomiędzy zmierzoną wartością napięcia wyjściowego a wartością
teoretyczną, którą wyznacza linia poprowadzona przez początek i koniec zakresu przetwarzania. Jako błąd
nieliniowości całkowej podaje się największą z wyznaczonych różnic.
Czas ustalania – czas po którym napięcie wyjściowe ustali się wewnątrz zakresu ±½ LSB przy
maksymalnej zmianie słowa kodowego (z 0000 0000b na 1111 1111b i odwrotnie).
Szybkość ustalania odpowiedzi – maksymalna szybkość narastania bądź opadania napięcia
wyjściowego.
U ODN
255
, UFS = UODN = 256 ⋅ Q, UMAX =
⋅ UFS,
256
256
D
⋅ UODN; D-kod przetwornika (0÷255)
UWY = UZERA +
256
Q = LSB = UODN ⋅ 2–8 =
UWAGA! Powyższe wzory obowiązują wyłącznie dla przetworników 8-bitowych
Podstawowe parametry przetwornika c/a typu AD7224KN
Zasilanie symetryczne UZAS = 11.4 ÷ 16.5 V, USS = –5 V ±10%;
AGND = DGND = 0 V;
UODN = +2 V do (UZAS – 4 V)
Parametr
PARAMETRY STATYCZNE
Rozdzielczość
Dokładność względna
Nieliniowość całkowa
Wartość
Jednostka
Uwagi
8
±2
±1
bity
LSB max
LSB max
UZAS = ±15 V ± 5 %,
UODN = 10 V
Nieliniowość różniczkowa
Błąd skalowania
±1
±1,5
LSB max
LSB max
monolityczność gwarantowana
Współczynnik temperaturowy skali
Błąd zera
Współczynnik temperaturowy zera
±20
±30
±50
ppm/°C max
mV max
µV/°C typ
PARAMETRY DYNAMICZNE
Szybkość ustalania odpowiedzi
2,5
V/µs min
Czas ustalania
skok narastający
skok malejący
Szpilki napięciowe
Minimalna rezystancja obciążenia
5
7
50
2
µs max
µs max
nV⋅s typ
kΩ min
-40 ÷ +85
°C
Temperatura pracy
Temperatura przechowywania
-65 ÷ +150
°C
UZAS = 14 V÷16,5 V, UODN =10V
UODN=10 V
UODN=10 V
UODN=0 V
UWY=10 V
Część II: Badanie przetwornika a/c
Schemat stanowiska pomiarowego
Regulator
temperatury
Generator
sygnału
taktującego
Zasilacz
Zasilacz sieciowy
Takt
wejście
Zadajnik
napięcia
mierzonego
Napięcie
mierzone
wejście
Badany przetwornik
AD670JN
Wyprowadzenie
magistrali
Termostat
Magistrala
Zadajnik
napięcia
Zasilanie zewnętrzne
przetwornika
Napięcie zasilające przetwornik
Napięcie
mierzone
Napięcie
mierzone
Tester przetwornika
A/C
V
Oscyloskop
Pole odczytowe
Napięcie
mierzone
wyjście
Status
wyjście
Ch1
Rys. 1 Schemat blokowy testera przetworników a/c
+
Ch2
Rys. 2 Schemat blokowy stanowiska do badania
przetwornika a/c
Słowo
wyjściowe
Output
4,5V - 5,5V
Output
Status
Takt
zewnętrzny
Generator
Bufor wyjściowy
-
V
0-2,55V
AD670JN
Int.
Napięcie mierzone
2
Output
Ext.
Zasilanie przetwornika
TTL
Moduł przetwornika
Status
Int.
1
0-2,55V
Ext.
Input
Stanowisko laboratoryjne
do badania przetworników
Napięcie Mierzone
On
Grzanie
Gotowe
-2q
A/C
Int.
wyk. Marcin Sikorski
TTL
Ext.
Input
Off
-q
-0,5q
Termostat
0,5q
q
2q
Uwe
AiR SP 2005
Taktowanie
-1
D7
D6
D5
D4
D3
D2
D1
D0
-2
Taktowanie ręczne
Zadajnik napięcia
mierzonego
Rys. 3 Widok płyty czołowej testera do badania przetwornika
a/c
Rys. 4 Charakterystyka przykładowego
przetwornika a/c uwzględniająca momenty
przełączeń
Offset Errors
THE IDEAL TRANSFER FUNCTION (ADC)
Digital Output
Code
Conversion Code
4.5 • 5.5
101
3.5 • 4.5
100
Center
011
011
010
1.5 • 2.5
010
0.5 • 1.5
001
0 • 0.5
000
001
Actual
Diagram
Step Width (1 LSB)
+1/2 LSB
0
1
2
3
0
Ideal
Diagram
1
Actual
Offset Point
Offset Error
(+1 1/4 LSB)
0
0
1
2
3
Analog Output Value
1
2
3
4
Inherent Quantization Error (±1/2 LSB)
(a)
Measured
Gain
010
Best Fit
Straight
Line
001
Analog Output Value (LSB)
Input
Ramp
Ideal
Diagram
(b)
Digital
Output
Error
3
Measured
Data
2
Ideal
Diagram
1
Analog Output
Value (LSB)
0…111
7
0…110
6
0…101
5
4
0…100
Total Error
At Step 0…101
(-1 1/4 LSB)
0…011
Actual
Diagram
3
0
2
3
Analog Output Value
Total Error
At Step 0…001
(1/2 LSB)
0…001
000
001
010
Digital Input Code
Total Error
At Step 0…011
(1 1/4 LSB)
2
0…010
000
011
1
0…000
0
0…000
0
1
2
3
4
5
6
7
0…100
0…010
0…001
0…011
Analog Input Value (LSB )
ADC
(b)
0…110
0…101
0…111
0…101
Digital Input Code
(a) ADC
(a)
DAC
Absolute Accuracy (Total) Error
Measured
Gain
Best Fit
Straight
Line
ADC
VLSI Analog Microelectronics (ESS)
Elements of Transfer Diagram for an Ideal Linear ADC
Gain Errors
011
Offset Error
(+1 1/4 LSB)
Analog Input Value
5
000
001
010
Nominal
Digital Input Code
Offset Point
Actual
Offset Point
Nominal
Offset Point
-1/2 LSB
Analog and Mixed-Signal Center (ESS)
1
2
000
4
5
Midstep Value of
011
+1/2 LSB
011
3
Analog Input Value
Quantization
Error
Digital Output Code
Ideal
Diagram
010
001
000
0
Input
Ramp
011
100
2.5 • 3.5
Actual
Diagram
101
Digital Output
Code
Digital Output Code
Range of
Analog Input
Values
Ideal Straight Line
0…101
(b) DAC
The absolute accuracy or total error of an ADC as shown in Figure is the maximum value of the difference between an analog value
and the ideal midstep value. It includes offset, gain, and integral linearity errors and also the quantization error in the case of an
ADC.
DAC
Analog and Mixed Signal Center, TAMU (ESS)
Integral Nonlinearity (INL) Error
Differential Nonlinearity (DNL)
111
7
010
6
Ideal
Transition
101
Digital Output Code
The integral non-linearity depicts a possible distortion of the input-output
transfer characteristic and leads to harmonic distortion.
Actual
Transition
100
At Transition
011/100
(-1/2 LSB)
011
010
End-Point Lin. Error
001
5
4
At Step
011 (1/2 LSB)
3
0
1
2
3
4
5
Analog Input Value (LSB)
(a) ADC
6
7
0…110
6
0…101
5
0…100
4
Differential
Linearity Error
(1/2 LSB)
0…011
End-Point Lin. Error
0…010
At Step
001 (1/4 LSB)
Differential
Linearity Error
(-1/2 LSB)
1 LSB
001
010
011
100
101
010
111
1 LSB
0
0
1
2
3
4
Differential Linearity
Error (+1/4 LSB)
5
0…000
0…010
0…001
Digital Input Code
(b) DAC
3
1
0…000
000
1 LSB
Differential
Linearity Error
(-1/4 LSB)
2
0…001
0
000
Analog Output
Value (LSB)
1 LSB
2
1
At Transition
001/010 (-1/4 LSB)
Digital
Output
Code
(a) ADC
Digital Input Code
End-Point Linearity Error of a Linear 3-bit Natural Binary-Coded ADC or DAC
(Offset Error and Gain Error are Adjusted to the Value Zero)
(b) DAC
Differential Linearity Error of a Linear ADC or DAC
Analog and Mixed-Signal Center (ESS)
0…100
0…011
Analog Input Value (LSB)
0…101
SELECTED PAGES ONLY!
a
FEATURES
8-Bit CMOS DAC with Output Amplifiers
Operates with Single or Dual Supplies
Low Total Unadjusted Error:
Less Than 1 LSB Over Temperature
Extended Temperature Range Operation
mP-Compatible with Double Buffered Inputs
Standard 18-Pin DIPs, and 20-Terminal Surface
Mount Package and SOIC Package
LC2MOS
8-Bit DAC with Output Amplifiers
AD7224
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7224 is a precision 8-bit voltage-output, digital-toanalog converter, with output amplifier and double buffered
interface logic on a monolithic CMOS chip. No external trims
are required to achieve full specified performance for the part.
1. DAC and Amplifier on CMOS Chip
The single-chip design of the 8-bit DAC and output amplifier
is inherently more reliable than multi-chip designs. CMOS
fabrication means low power consumption (35 mW typical
with single supply).
The double buffered interface logic consists of two 8-bit registers–an input register and a DAC register. Only the data held in
the DAC registers determines the analog output of the converter. The double buffering allows simultaneous update in a
system containing multiple AD7224s. Both registers may be
made transparent under control of three external lines, CS, WR
and LDAC. With both registers transparent, the RESET line
functions like a zero override; a useful function for system calibration cycles. All logic inputs are TTL and CMOS (5 V) level
compatible and the control logic is speed compatible with most
8-bit microprocessors.
Specified performance is guaranteed for input reference voltages
from +2 V to +12.5 V when using dual supplies. The part is also
specified for single supply operation using a reference of +10 V.
The output amplifier is capable of developing +10 V across a
2 kΩ load.
The AD7224 is fabricated in an all ion-implanted high speed
Linear Compatible CMOS (LC2MOS) process which has been
specifically developed to allow high speed digital logic circuits
and precision analog circuits to be integrated on the same chip.
2. Low Total Unadjusted Error
The fabrication of the AD7224 on Analog Devices Linear
Compatible CMOS (LC2MOS) process coupled with a novel
DAC switch-pair arrangement, enables an excellent total unadjusted error of less than 1 LSB over the full operating temperature range.
3. Single or Dual Supply Operation
The voltage-mode configuration of the AD7224 allows operation from a single power supply rail. The part can also be operated with dual supplies giving enhanced performance for
some parameters.
4. Versatile Interface Logic
The high speed logic allows direct interfacing to most microprocessors. Additionally, the double buffered interface enables simultaneous update of the AD7224 in multiple DAC
systems. The part also features a zero override function.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD7224–SPECIFICATIONS
DUAL SUPPLY
(VDD = 11.4 V to 16.5 V, VSS = –5 V 6 10%; AGND = DGND = O V; VREF = +2 V to (VDD – 4 V)1 unless otherwise noted.
All specifications TMIN to TMAX unless otherwise noted.)
Parameter
K, B, T
Versions2
L, C, U
Versions2
Units
STATIC PERFORMANCE
Resolution
Total Unadjusted Error
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
Full-Scale Temperature Coefficient
Zero Code Error
Zero Code Error Temperature Coefficient
8
±2
±1
±1
± 3/2
± 20
± 30
± 50
8
±1
± 1/2
±1
±1
± 20
± 20
± 30
Bits
LSB max
LSB max
LSB max
LSB max
ppm/°C max
mV max
µV/°C typ
REFERENCE INPUT
Voltage Range
Input Resistance
Input Capacitance3
2 to (VDD – 4)
8
100
2 to (VDD – 4)
8
100
V min to V max
kΩ min
pF max
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current
Input Capacitance3
Input Coding
2.4
0.8
±1
8
Binary
2.4
0.8
±1
8
Binary
V min
V max
µA max
pF max
2.5
2.5
V/µs min
5
7
50
2
5
7
50
2
µs max
µs max
nV secs typ
kΩ min
VREF = +10 V; Settling Time to ± 1/2 LSB
VREF = +10 V; Settling Time to ± 1/2 LSB
VREF = 0 V
VOUT = +10 V
11.4/16.5
4.5/5.5
11.4/16.5
4.5/5.5
V min/V max
V min/V max
For Specified Performance
For Specified Performance
4
6
4
6
mA max
mA max
Outputs Unloaded; VIN = VINL or VINH
3
5
3
5
mA max
mA max
90
90
90
90
ns min
ns min
Chip Select/Load DAC Pulse Width
90
90
90
90
ns min
ns min
Write/Reset Pulse Width
0
0
0
0
ns min
ns min
Chip Select/Load DAC to Write Setup Time
0
0
0
0
ns min
ns min
Chip Select/Load DAC to Write Hold Time
90
90
90
90
ns min
ns min
Data Valid to Write Setup Time
10
10
10
10
ns min
ns min
Data Valid to Write Hold Time
DYNAMIC PERFORMANCE
Voltage Output Slew Rate3
Voltage Output Settling Time3
Positive Full-Scale Change
Negative Full-Scale Change
Digital Feedthrough
Minimum Load Resistance
POWER SUPPLIES
VDD Range
VSS Range
IDD
@ 25°C
TMIN to TMAX
ISS
@ 25°C
TMIN to TMAX
SWITCHING CHARACTERISTICS3, 4
t1
@ 25°C
TMIN to TMAX
t2
@ 25°C
TMIN to TMAX
t3
@ 25°C
TMIN to TMAX
t4
@ 25°C
TMIN to TMAX
t5
@ 25°C
TMIN to TMAX
t6
@ 25°C
TMIN to TMAX
Conditions/Comments
VDD = +15 V ± 5%, VREF = +10 V
Guaranteed Monotonic
VDD = 14 V to 16.5 V, VREF = +10 V
Occurs when DAC is loaded with all 1s.
VIN = 0 V or VDD
NOTES
1
Maximum possible reference voltage.
2
Temperature ranges are as follows:
K, L Versions: –40°C to +85°C
B, C Versions: –40°C to +85°C
T, U Versions: –55°C to +125°C
3
Sample Tested at 25°C by Product Assurance to ensure compliance.
4
Switching characteristics apply for single and dual supply operation.
Specifications subject to change without notice.
–2–
REV. B
AD7224
ABSOLUTE MAXIMUM RATINGS 1
ORDERING GUIDE
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +24 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD
Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD + 0.3 V
VREF to AGND . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
VOUT to AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature
Commercial (K, L Versions) . . . . . . . . . . . –40°C to +85°C
Industrial (B, C Versions) . . . . . . . . . . . . . –40°C to +85°C
Extended (T, U Versions) . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
The outputs may be shorted to AGND provided that the power dissipation of the
package is not exceeded. Typically short circuit current to AGND is 60 mA.
Model1
Temperature
Range
Total
Unadjusted
Error (LSB)
Package
Option2
AD7224KN
AD7224LN
AD7224KP
AD7224LP
AD7224KR-1
AD7224LR-1
AD7224KR-18
AD7224LR-18
AD7224BQ
AD7224CQ
AD7224TQ
AD7224UQ
AD7224TE
AD7224UE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
± 2 max
± 1 max
± 2 max
± 1 max
± 2 max
± 1 max
± 2 max
± 1 max
± 2 max
± 1 max
± 2 max
± 1 max
± 2 max
± 1 max
N-18
N-18
P-20A
P-20A
R-20
R-20
R-18
R-18
Q-18
Q-18
Q-18
Q-18
E-20A
E-20A
NOTES
1
To order MIL-STD-883 processed parts, add /883B to part number.
Contact your local sales office for military data sheet.
2
E = Leadless Ceramic Chip Carrier; N = Plastic DIP;
P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7224 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATIONS
DIP and SOIC
(SOIC)
VSS
1
18
VDD
VOUT
2
17
RESET
(SOIC)
VSS
1
18
VDD
VOUT
2
17
RESET
VSS
1
20
VOUT
2
19 RESET
VDD
VREF
3
16 LDAC
VREF
3
AGND
4
15
WR
AGND
4
DGND
5
CS
DGND
5
(MSB) DB7
6
14
TOP VIEW
(Not to Scale)
13
(MSB) DB7
6
DB6
7
12 DB1
DB6
7
12 DB1
DB6
7
14 DB1
DB5
8
11 DB2
DB5
8
11 DB2
DB5
8
13 DB2
DB4
9
10 DB3
DB4
9
10 DB3
DB4
9
12 DB3
AD7224
DB0 (LSB)
16 LDAC
VREF
3
15
WR
AGND
4
14
TOP VIEW
(Not to Scale)
13
CS
DGND
5
(MSB) DB7
6
AD7224
R-18
18 LDAC
AD7224
R-20
DB0 (LSB)
16 CS
TOP VIEW
(Not to Scale) 15 DB0 (LSB)
NC 10
VDD
RESET
NC
1
20 19
VREF
4
AD7224
AGND
5
AD7224
17 WR
TOP VIEW
(Not to Scale)
16 CS
DGND
6
16 CS
(MSB) DB7
7
TOP VIEW
(Not to Scale)
DB6
8
NC = NO CONNECT
15 DB0 (LSB)
14 DB1
10 11 12 13
DB2
9
NC
DB2
NC
10 11 12 13
DB3
9
DB4
14 DB1
DB5
DB6 8
DB3
15 DB0 (LSB)
18 LDAC
DB4
18 LDAC
(MSB) DB7 7
2
DB5
DGND 6
3
11 NC
NC = NO CONNECT
17 WR
VREF 4
AGND 5
VOUT
NC
1 20 19
VDD
VOUT
VSS
2
VSS
PLCC
RESET
LCCC
3
17 WR
NC = NO CONNECT
–4–
REV. B
AD7224
VOUT = D • VREF
TERMINOLOGY
TOTAL UNADJUSTED ERROR
Total Unadjusted Error is a comprehensive specification which
includes full-scale error, relative accuracy and zero code error.
Maximum output voltage is VREF – 1 LSB (ideal), where 1 LSB
(ideal) is VREF/256. The LSB size will vary over the VREF range.
Hence the zero code error, relative to the LSB size, will increase
as VREF decreases. Accordingly, the total unadjusted error,
which includes the zero code error, will also vary in terms of
LSBs over the VREF range. As a result, total unadjusted error is
specified for a fixed reference voltage of +10 V.
RELATIVE ACCURACY
Relative Accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after allowing for zero code error and full-scale error and is normally
expressed in LSBs or as a percentage of full-scale reading.
where D is a fractional representation of the digital input code
and can vary from 0 to 255/256.
OP-AMP SECTION
The voltage-mode D/A converter output is buffered by a unity
gain noninverting CMOS amplifier. This buffer amplifier is
capable of developing +10 V across a 2 kΩ load and can drive
capacitive loads of 3300 pF.
The AD7224 can be operated single or dual supply resulting in
different performance in some parameters from the output amplifier. In single supply operation (VSS = 0 V = AGND) the sink
capability of the amplifier, which is normally 400 µA, is reduced
as the output voltage nears AGND. The full sink capability of
400 µA is maintained over the full output voltage range by tying
VSS to –5 V. This is indicated in Figure 2.
500
DIFFERENTIAL NONLINEARITY
VSS = –5V
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB max over
the operating temperature range ensures monotonicity.
ISINK – µA
400
DIGITAL FEEDTHROUGH
Digital Feedthrough is the glitch impulse transferred to the output due to a change in the digital input code. It is specified in
nV secs and is measured at VREF = 0 V.
0
0
Full-Scale Error is defined as:
Measured Value – Zero Code Error – Ideal Value
D/A SECTION
The AD7224 contains an 8-bit voltage-mode digital-to-analog
converter. The output voltage from the converter has the same
polarity as the reference voltage, allowing single supply operation. A novel DAC switch pair arrangement on the AD7224 allows a reference voltage range from +2 V to +12.5 V.
The DAC consists of a highly stable, thin-film, R-2R ladder and
eight high speed NMOS single pole, double-throw switches.
The simplified circuit diagram for this DAC is shown in
Figure 1.
VREF
R
R
VOUT
2R
2R
2R
2R
DB0
DB0
DB0
DB0
SHOWN FOR ALL 1's ON DAC
AGND
Figure 1. D/A Simplified Circuit Diagram
The input impedance at the VREF pin is code dependent and can
vary from 8 kΩ minimum to infinity. The lowest input impedance occurs when the DAC is loaded with the digital code
01010101. Therefore, it is important that the reference presents
a low output impedance under changing load conditions. The
nodal capacitance at the reference terminals is also code dependent and typically varies from 25 pF to 50 pF.
The VOUT pin can be considered as a digitally programmable
voltage source with an output voltage of:
REV. B
2
4
6
VOUT – Volts
8
10
Figure 2. Variation of ISINK with VOUT
CIRCUIT INFORMATION
2R
VDD = +15V
TA = 25°C
VSS = 0V
200
100
FULL-SCALE ERROR
R
300
Settling-time for negative-going output signals approaching
AGND is similarly affected by VSS. Negative-going settling-time
for single supply operation is longer than for dual supply operation. Positive-going settling-time is not affected by VSS.
Additionally, the negative VSS gives more headroom to the output amplifier which results in better zero code performance and
improved slew-rate at the output, than can be obtained in the
single supply mode.
DIGITAL SECTION
The AD7224 digital inputs are compatible with either TTL or
5 V CMOS levels. All logic inputs are static-protected MOS
gates with typical input currents of less than 1 nA. Internal input protection is achieved by an on-chip distributed diode between DGND and each MOS gate. To minimize power supply
currents, it is recommended that the digital input voltages be
driven as close to the supply rails (VDD and DGND) as practically possible.
INTERFACE LOGIC INFORMATION
Table I shows the truth table for AD7224 operation. The part
contains two registers, an input register and a DAC register. CS
and WR control the loading of the input register while LDAC
and WR control the transfer of information from the input register to the DAC register. Only the data held in the DAC register
will determine the analog output of the converter.
All control signals are level-triggered and therefore either or
both registers may be made transparent; the input register by
keeping CS and WR “LOW”, the DAC register by keeping
LDAC and WR “LOW”. Input data is latched on the rising
edge of WR.
–5–
AD7224
BIPOLAR OUTPUT OPERATION
VIN
The AD7224 can be configured to provide bipolar output operation using one external amplifier and two resistors. Figure 6
shows a circuit used to implement offset binary coding. In this
case
VREF
VDD
VOUT
AGND
DAC
VIN

 R2 
R2 
V O = 1 +
 • ( D V REF ) – 
 • (V REF )

 R1 
R1 
AD7224
VBIAS
With R1 = R2
VSS
VO = (2 D – 1) • VREF
where D is a fractional representation of the digital word in
the DAC register.
Mismatch between R1 and R2 causes gain and offset errors;
therefore, these resistors must match and track over temperature. Once again, the AD7224 can be operated in single supply
or from positive/negative supplies. Table III shows the digital
code versus output voltage relationship for the circuit of Figure
6 with R1 = R2.
DGND
Figure 7. AGND Bias Circuit
MICROPROCESSOR INTERFACE
A15
ADDRESS BUS
A8
ADDRESS
DECODE
8085A
8088
CS
LDAC
AD7224*
WR
VREF
VREF
VDD
R1
3
DB7
DATA
(8-BIT)
R2
ALE
+15V
AD7
AD0
LATCH
EN
DB7
DB0
ADDRESS DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
VOUT
DB0
CS
WR
DAC
VOUT
WR
AD7224
LDAC
Figure 8. AD7224 to 8085A/8088 Interface
+15V
A15
R1, R2 = 10kΩ ±0.1%
RESET
ADDRESS BUS
A0
VSS
AGND
DGND
6809
6502
R/W
ADDRESS
DECODE
CS
LDAC
EN
AD7224*
Figure 6. Bipolar Output Circuit
Table III. Bipolar (Offset Binary) Code Table
DAC Register Contents
MSB
LSB
1111
1111
1000
0001
E OR φ2
WR
D7
E OR φ2
D0
DB7
DB0
D7
D0
Analog Output
DATA BUS
 127 
+V REF 

 128 
 1 
+V REF 

 128 
Figure 9. AD7224 to 6809/6502 Interface
A15
ADDRESS BUS
A0
1000
0000
0V
CS
Z-80
0111
0000
0000
1111
0001
0000
 1 
–V REF 

 128 
 127 
–V REF 

 128 
 128 
–V REF 
 = –V REF
 128 
LDAC
AD7224*
WR
WR
DB7
DB0
D7
D0
DATA BUS
Figure 10. AD7224 to Z-80 Interface
AGND BIAS
The AD7224 AGND pin can be biased above system GND
(AD7224 DGND) to provide an offset “zero” analog output
voltage level. Figure 7 shows a circuit configuration to achieve
this. The output voltage, VOUT, is expressed as:
VOUT = VBIAS + D • (VIN)
where D is a fractional representation of the digital word in
DAC register and can vary from 0 to 255/256.
A23
ADDRESS BUS
A1
68008
ADDRESS
DECODE
R/W
CS
LDAC
WR
AD7224*
DTACK
DB7
DB0
D7
For a given VIN, increasing AGND above system GND will reduce the effective VDD–VREF which must be at least 4 V to ensure specified operation. Note that VDD and VSS for the AD7224
must be referenced to DGND.
REV. B
ADDRESS
DECODE
D0
DATA BUS
Figure 11. AD7224 to 68008 Interface
–7–
a
FEATURES
Complete 8-Bit Signal Conditioning A/D Converter
Including Instrumentation Amp and Reference
Microprocessor Bus Interface
10 ms Conversion Speed
Flexible Input Stage: Instrumentation Amp Front End
Provides Differential Inputs and High Common-Mode
Rejection
No User Trims Required
No Missing Codes Over Temperature
Single +5 V Supply Operation
Convenient Input Ranges
20-Pin DIP or Surface-Mount Package
Low Cost Monolithic Construction
MIL-STD-883B Compliant Versions Available
GENERAL DESCRIPTION
The AD670 is a complete 8-bit signal conditioning analogto-digital converter. It consists of an instrumentation amplifier
front end along with a DAC, comparator, successive approximation register (SAR), precision voltage reference, and a threestate output buffer on a single monolithic chip. No external
components or user trims are required to interface, with full
accuracy, an analog system to an 8-bit data bus. The AD670
will operate on the +5 V system supply. The input stage provides differential inputs with excellent common-mode rejection
and allows direct interface to a variety of transducers.
The device is configured with input scaling resistors to permit
two input ranges: 0 mV to 255 mV (1 mV/LSB) and 0 to 2.55 V
(10 mV/LSB). The AD670 can be configured for both unipolar
and bipolar inputs over these ranges. The differential inputs and
common-mode rejection of this front end are useful in applications such as conversion of transducer signals superimposed on
common-mode voltages.
The AD670 incorporates advanced circuit design and proven
processing technology. The successive approximation function
is implemented with I2L (integrated injection logic). Thin-film
SiCr resistors provide the stability required to prevent missing
codes over the entire operating temperature range while laser
wafer trimming of the resistor ladder permits calibration of the
device to within ± 1 LSB. Thus, no user trims for gain or offset
are required. Conversion time of the device is 10 µs.
Low Cost Signal
Conditioning 8-Bit ADC
AD670
FUNCTIONAL BLOCK DIAGRAM
The S grade is also available with optional processing to
MIL-STD-883 in 20-pin ceramic DIP or 20-terminal LCC
packages. The Analog Devices Military Products Databook
should be consulted for detailed specifications.
PRODUCT HIGHLIGHTS
1. The AD670 is a complete 8-bit A/D including three-state
outputs and microprocessor control for direct connection to
8-bit data buses. No external components are required to
perform a conversion.
2. The flexible input stage features a differential instrumentation amp input with excellent common-mode rejection. This
allows direct interface to a variety of transducers without
preamplification.
3. No user trims are required for 8-bit accurate performance.
4. Operation from a single +5 V supply allows the AD670 to
run off of the microprocessor’s supply.
5. Four convenient input ranges (two unipolar and two bipolar)
are available through internal scaling resistors: 0 mV to
255 mV (1 mV/LSB) and 0 V to 2.55 V (10 mV/LSB).
6. Software control of the output mode is provided. The user
can easily select unipolar or bipolar inputs and binary or 2s
complement output codes.
The AD670 is available in four package types and five grades.
The J and K grades are specified over 0°C to +70°C and come
in 20-pin plastic DIP packages or 20-terminal PLCC packages.
The A and B grades (–40°C to +85°C) and the S grade (–55°C
to +125°C) come in 20-pin ceramic DIP packages.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD670–SPECIFICATIONS
(@ VCC = +5 V and +258C, unless otherwise noted)
Model
Min
OPERATING TEMPERATURE RANGE
0
RESOLUTION
8
AD670J
Typ
Max
Min
+70
0
AD670K
Typ
Max
+70
8
Units
°C
Bit
CONVERSION TIME
10
10
µs
RELATIVE ACCURACY
TMIN to TMAX
61/2
6l/2
61/4
61/2
LSB
LSB
DIFFERENTIAL LINEARITY ERROR1
TMIN to TMAX
GUARANTEED NO MISSING CODES ALL GRADES
GAIN ACCURACY
@ +25°C
TMIN to TMAX
61.5
62.0
60.75
61.0
LSB
LSB
UNIPOLAR ZERO ERROR
@ +25°C
TMIN to TMAX
61.5
62.0
60.75
61.0
LSB
LSB
BIPOLAR ZERO ERROR
@ +25°C
TMIN to TMAX
61.5
62.0
60.75
61.0
LSB
LSB
ANALOG INPUT RANGES
DIFFERENTIAL (–VIN to +VIN)
Low Range
0 to +255
–128 to +127
0 to +2.55
–1.28 to +1.27
High Range
ABSOLUTE (Inputs to Power GND)
Low Range TMIN to TMAX
High Range TMIN to TMAX
–0.150
–1.50
BIAS CURRENT (255 mV RANGE)
TMIN to TMAX
200
OFFSET CURRENT (255 mV RANGE)
TMIN to TMAX
2.55 V RANGE INPUT RESISTANCE
VCC – 3.4
VCC
–0.150
–1.50
500
40
200
200
8.0
2.55 V RANGE FULL-SCALE MATCH
+ AND – INPUT
0 to +255
–128 to +127
0 to +2.55
–1.28 to +1.27
12.0
40
8.0
± 1/2
mV
mV
V
V
VCC – 3.4
VCC
V
V
500
nA
200
nA
12.0
kΩ
± 1/2
LSB
COMMON-MODE REJECTION
RATIO (255 mV RANGE)
1
1
LSB
COMMON-MODE REJECTION
RATIO (2.55 V RANGE)
1
1
LSB
5.5
45
0.015
V
mA
% of FS/%
POWER SUPPLY
Operating Range
Current ICC
Rejection Ratio TMIN to TMAX
DIGITAL OUTPUTS
SINK CURRENT (VOUT = 0.4 V)
TMIN to TMAX
SOURCE CURRENT (VOUT = 2.4 V)
TMIN to TMAX
4.5
5.5
45
0.015
30
1.6
mA
0.5
0.5
mA
640
OUTPUT CAPACITANCE
DIGITAL INPUT CURRENT
(0 ≤ VIN ≤ +5 V)
IINL
IINH
INPUT CAPACITANCE
30
1.6
THREE-STATE LEAKAGE CURRENT
DIGITAL INPUT VOLTAGE
VINL
VINH
4.5
640
5
5
0.8
2.0
pF
0.8
2.0
–100
–100
+100
10
+100
10
µA
V
V
µA
µA
pF
NOTES
1
Tested at VCC = 4 5 V, 5.0 V and 5.5 V.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications
are guaranteed although only those shown in boldface are tested on all production units.
Specifications subject to change without notice.
–2–
REV. A
AD670
ABSOLUTE MAXIMUM RATINGS*
VCC to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +7.5 V
Digital Inputs (Pins 11–15) . . . . . . . . . . . –0.5 V to VCC +0.5 V
Digital Outputs (Pins 1–9) . Momentary Short to VCC or Ground
Analog Inputs (Pins 16–19) . . . . . . . . . . . . . . . –30 V to +30 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at them or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Figure 1. AD670 Block Diagram and Terminal
Configuration (AII Packages)
ORDERING GUIDE
Model1
Temperature
Range
Relative Accuracy
@ +258C
Gain Accuracy
@ +258C
Package Option2
AD670JN
AD670JP
AD670KN
AD670KP
AD670AD
AD670BD
AD670SD
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
± 1/2 LSB
± 1/2 LSB
± 1/4 LSB
± 1/4 LSB
± 1/2 LSB
± 1/4 LSB
± 1/2 LSB
± 1.5 LSB
± 1.5 LSB
± 0.75 LSB
± 0.75 LSB
± 1.5 LSB
± 0.75 LSB
± 1.5 LSB
Plastic DIP (N-20)
PLCC (P-20A)
Plastic DIP (N-20)
PLCC (P-20A)
Ceramic DIP (D-20)
Ceramic DIP (D-20)
Ceramic DIP (D-20)
NOTES
1
For details on grade and package offerings screened in accordance with MIL-STD-883 refer to the Analog Devices
Military Products Databook.
2
D = Ceramic DIP; N = Plastic DIP; P = Plastic Leaded Chip Carrier.
CIRCUIT OPERATION/FUNCTIONAL DESCRIPTION
The AD670 is a functionally complete 8-bit signal conditioning
A/D converter with microprocessor compatibility. The input
section uses an instrumentation amplifier to accomplish the
voltage to current conversion. This front end provides a high
impedance, low bias current differential amplifier. The common-mode range allows the user to directly interface the device
to a variety of transducers.
The AID conversions are controlled by R/W, CS, and CE. The
R/W line directs the converter to read or start a conversion. A
minimum write/start pulse of 300 ns is required on either CE or
CS. The STATUS line goes high, indicating that a conversion is
in process. The conversion thus begun, the internal 8-bit DAC
is sequenced from MSB to LSB using a novel successive approximation technique. In conventional designs, the DAC is
stepped through the bits by a clock. This can be thought of as a
static design since the speed at which the DAC is sequenced is
determined solely by the clock. No clock is used in the AD670.
Instead, a “dynamic SAR” is created consisting of a string of inverters with taps along the delay line. Sections of the delay line
between taps act as one shots. The pulses are used to set and reset the DAC’s bits and strobe the comparator. When strobed,
the comparator then determines whether the addition of each
successively weighted bit current causes the DAC current sum
to be greater or less than the input current. If the sum is less,
the bit is turned off. After all bits are tested, the SAR holds an
8-bit code representing the input signal to within 1/2 LSB
accuracy. Ease of implementation and reduced dependence on
process related variables make this an attractive approach to a
successive approximation design.
The SAR provides an end-of-conversion signal to the control
logic which then brings the STATUS line low. Data outputs remain in a high impedance state until R/W is brought high with
CE and CS low and allows the converter to be read. Bringing
CE or CS high during the valid data period ends the read cycle.
The output buffers cannot be enabled during a conversion. Any
convert start commands will be ignored until the conversion
cycle is completed; once a conversion cycle has been started it
cannot be stopped or restarted.
The AD670 provides the user with a great deal of flexibility by
offering two input spans and formats and a choice of output
codes. Input format and input range can each be selected. The
BPO/UPO pin controls a switch which injects a bipolar offset
current of a value equal to the MSB less 1/2 LSB into the summing node of the comparator to offset the DAC output. Two
precision 10 to 1 attenuators are included on board to provide
input range selection of 0 V to 2.55 V or 0 mV to 255 mV. Additional ranges of –1.28 V to 1.27 V and –128 mV to 127 mV
are possible if the BPO/UPO switch is high when the conversion
is started. Finally, output coding can be chosen using the FORMAT pin when the conversion is started. In the bipolar mode
and with a Logic 1 on FORMAT, the output is in two’s complement; with a Logic 0, the output is offset binary.
–4–
REV. A
AD670
CONNECTING THE AD670
The AD670 has been designed for ease of use. All active components required to perform a complete A/D conversion are on
board and are connected internally. In addition, all calibration
trims are performed at the factory, assuring specified accuracy
without user trims. There are, however, a number of options
and connections that should be considered to obtain maximum
flexibility from the part.
INPUT CONNECTIONS
Standard connections are shown in the figures that follow. An
input range of 0 V to 2.55 V may be configured as shown in Figure 2a. This will provide a one LSB change for each 10 mV of
input change. The input range of 0 mV to 255 mV is configured
as shown in Figure 2b. In this case, each LSB represents 1 mV
of input change. When unipolar input signals are used, Pin 11,
BPO/UPO, should be grounded. Pin 11 selects the input format
for either unipolar or bipolar signals. Figures 3a and 3b show
the input connections for bipolar signals. Pin 11 should be tied
to +VCC for bipolar inputs.
Although the instrumentation amplifier has a differential input,
there must be a return path to ground for the bias currents. If it
is not provided, these currents will charge stray capacitances
and cause internal circuit nodes to drift uncontrollably causing
the digital output to change. Such a return path is provided in
Figures 2a and 3a (larger input ranges) since the 1k resistor leg
is tied to ground. This is not the case for Figures 2b and 3b (the
lower input ranges). When connecting the AD670 inputs to
floating sources, such as transformers and ac-coupled sources,
there must still be a dc path from each input to common. This
can be accomplished by connecting a 10 kΩ resistor from each
input to ground.
3a. ± 1.28 V Range
3b. ± 128 mV Range
NOTE: PIN 11, BPO/UPO SHOULD BE HIGH WHEN
CONVERSION IS STARTED.
Figure 3. Bipolar Input Connections
Bipolar Operation
Through special design of the instrumentation amplifier, the
AD670 accommodates input signal excursions below ground,
even though it operates from a single 5 V supply. To the user,
this means that true bipolar input signals can be used without
the need for any additional external components. Bipolar signals
can be applied differentially across both inputs, or one of the inputs can be grounded and a bipolar signal applied to the other.
Common-Mode Performance
2a. 0 V to 2.55 V (10 mV/LSB)
2b. 0 mV to 255 mV (1 mV/LSB)
NOTE: PIN 11, BPO/UPO SHOULD BE LOW WHEN
CONVERSION IS STARTED.
The AD670 is designed to reject dc and ac common-mode voltages. In some applications it is useful to apply a differential input signal VIN in the presence of a dc common-mode voltage
VCM. The user must observe the absolute input signal limits
listed in the specifications, which represent the maximum voltage VIN + VCM that can be applied to either input without affecting proper operation. Exceeding these limits (within the range of
absolute maximum ratings), however, will not cause permanent
damage.
The excellent common-mode rejection of the AD670 is due to
the instrumentation amplifier front end, which maintains the
differential signal until it reaches the output of the comparator.
In contrast to a standard operational amplifier, the instrumentation amplifier front end provides significantly improved CMRR
over a wide frequency range (Figure 4a).
Figure 2. Unipolar Input Connections
REV. A
–5–
AD670
Table I. AD670 Input Selection/Output Format Truth Table
Figure 4a. CMRR Over Frequency
BPO/UPO
FORMAT
INPUT RANGE/
OUTPUT FORMAT
0
1
0
1
0
0
1
1
Unipolar/Straight Binary
Bipolar/Offset Binary
Unipolar/2s Complement
Bipolar/2s Complement
+VIN
–VIN
DIFF
VIN
STRAIGHT BINARY
(FORMAT = 0, BPO/UPO = 0)
0
128 mV
255 mV
255 mV
128 mV
128 mV
0
0
0
255 mV
127 mV
–127 mV
0
128 mV
255 mV
0
1 mV
255 mV
0000 0000
1000 0000
1111 1111
0000 0000
0000 0001
1111 1111
Figure 5a. Unipolar Output Codes (Low Range)
Figure 4b. AD670 Input Rejects Common-Mode
Ground Noise
Good common-mode performance is useful in a number of situations. In bridge-type transducer applications, such performance
facilitates the recovery of differential analog signals in the presence of a dc common-mode or a noisy electrical environment.
High frequency CMRR also becomes important when the analog signal is referred to a noisy, remote digital ground. In each
case, the CMRR specification of the AD670 allows the integrity
of the input signal to be preserved.
The AD670’s common-mode voltage tolerance allows great
flexibility in circuit layout. Most other A/D converters require
the establishment of one point as the analog reference point.
This is necessary in order to minimize the effects of parasitic
voltages. The AD670, however, eliminates the need to make the
analog ground reference point and A/D analog ground one and
the same. Instead, a system such as that shown in Figure 4b is
possible as a result of the AD670’s common-mode performance.
The resistors and inductors in the ground return represent unavoidable system parasitic impedances.
+VIN
–VIN
DIFF
VIN
0
127 mV
1.127 V
255 mV
128 mV
127 mV
127 mV
–128 mV
0
0
1.000 V
255 mV
127 mV
128 mV
255 mV
0
0
127 mV
127 mV
0
1 mV
–1 mV
–128 mV
–128 mV
OFFSET BINARY 2s COMPLEMENT
(FORMAT = 0,
(FORMAT = 1,
BPO/UPO = 1)
BPO/UPO = 1)
1000 0000
1111 1111
1111 1111
1000 0000
1000 0001
0111 1111
0000 0000
0000 0000
0000 0000
0111 1111
0111 1111
0000 0000
0000 0001
1111 1111
1000 0000
1000 0000
Figure 5b. Bipolar Output Codes (Low Range)
Calibration
Because of its precise factory calibration, the AD670 is intended
to be operated without user trims for gun and offset; therefore,
no provisions have been made for such user trims. Figures 6a,
6b, and 6c show the transfer curves at zero and full scale for the
unipolar and bipolar modes. The code transitions are positioned
so that the desired value is centered at that code. The first LSB
transition for the unipolar mode occurs for an input of +1/2 LSB
(5 mV or 0.5 mV). Similarly, the MSB transition for the bipolar
mode is set at –1/2 LSB (–5 mV or –0.5 mV). The full scale
transition is located at the full scale value –1 1/2 LSB. These
values are 2.545 V and 254.5 mV.
Input/Output Options
Data output coding (2s complement vs. straight binary) is
selected using Pin 12, the FORMAT pin. The selection of
input format (bipolar vs. unipolar) is controlled using Pin 11,
BPO/UPO. Prior to a write/convert, the state of FORMAT and
BPO/UPO should be available to the converter. These lines may
be tied to the data bus and may be changed with each conversion if desired. The configurations are shown in Table I. Output
coding for representative signals in each of these configurations
is shown in Figure 5.
An output signal, STATUS, indicates the status of the conversion. STATUS goes high at the beginning of the conversion and
returns low when the conversion cycle has been completed.
6a. Unipolar Transfer Curve
–6–
REV. A
AD670
6b. Bipolar
Figure 7. Control Logic Block Diagram
Table II. AD670 Control Signal Truth Table
6c. Full Scale (Unipolar)
Figure 6. Transfer Curves
R/W
CS
CE
OPERATION
0
1
X
X
0
0
X
1
0
0
1
X
WRITE/CONVERT
READ
NONE
NONE
Timing
The AD670 is easily interfaced to a variety of microprocessors
and other digital systems. The following discussion of the timing
requirements of the AD670 control signals will provide the designer with useful insight into the operation of the device.
CONTROL AND TIMING OF THE AD670
Control Logic
The AD670 contains on-chip logic to provide conversion and
data read operations from signals commonly available in microprocessor systems. Figure 7 shows the internal logic circuitry of
the AD670. The control signals, CE, CS, and R/W control the
operation of the converter. The read or write function is determined by R/W when both CS and CE are low as shown in
Table II. If all three control inputs are held low longer than the
conversion time, the device will continuously convert until one
input, CE, CS, or R/W is brought high. The relative timing of
these signals is discussed later in this section.
Write/Convert Start Cycle
Figure 8 shows a complete timing diagram for the write/convert
start cycle. CS (chip select) and CE (chip enable) are active low
and are interchangeable signals. Both CS and CE must be low
for the converter to read or start a conversion. The minimum
pulse width, tW, on either CS or CE is 300 ns to start a
conversion.
Table III. AD670 TIMING SPECIFICATIONS
Symbol
Parameter
Min
@ +258C
Typ
Max
Units
700
10
ns
ns
ns
ns
ns
µs
WRITE/CONVERT START MODE
tW
tDS
tDH
tRWC
tDC
tC
Write/Start Pulse Width
Input Data Setup Time
Input Data Hold
Read/Write Setup Before Control
Delay to Convert Start
Conversion Time
300
200
10
0
READ MODE
tR
tSD
tTD
tDH
tDT
tRT
Read Time
Delay from Status Low to Data Read
Bus Access Time
Data Hold Time
Output Float Delay
R/W before CE or CS low
250
200
250
250
25
150
0
ns
ns
ns
ns
ns
ns
Boldface indicates parameters tested 100% unless otherwise noted. See Specifications page for explanation.
REV. A
–7–
AD670
STAND-ALONE OPERATION
The AD670 can be used in a “stand-alone” mode, which is useful in systems with dedicated input ports available. Two typical
conditions are described and illustrated by the timing diagrams
which follow.
Single Conversion, Single Read
Figure 8. Write/Convert Start Timing
When the AD670 is used in a stand-alone mode, CS and CE
should be tied together. Conversion will be initiated by bringing
R/W low. Within 700 ns, a conversion will begin. The R/W
pulse should be brought high again once the conversion has
started so that the data will be valid upon completion of the
conversion. Data will remain valid until CE and CS are brought
high to indicate the end of the read cycle or R/W goes low. The
timing diagram is shown in Figure 10.
The R/W line is used to direct the converter to start a conversion (R/W low) or read data (R/W high). The relative sequencing of the three control signals (R/W, CE, CS) is unimportant.
However, when all three signals remain low for at least 300 ns
(tW), STATUS will go high to signal that a conversion is taking
place.
Once a conversion is started and the STATUS line goes high,
convert start commands will be ignored until the conversion
cycle is complete. The output data buffer cannot be enabled
during a conversion.
Read Cycle
Figure 9 shows the timing for the data read operation. The data
outputs are in a high impedance state until a read cycle is initiated. To begin the read cycle, R/W is brought high. During a
read cycle, the minimum pulse length for CE and CS is a function of the length of time required for the output data to be
valid. The data becomes valid and is available to the data bus in
a maximum of 250 ns. This delay between the high impedance
state and valid data is the maximum bus access time or tTD.
Bringing CE or CS high during valid data ends the read cycle.
The outputs remain valid for a minimum of 25 ns (tDH) and return to the high impedance state after a delay, tDT, of 150 ns
maximum.
Figure 10. Stand-Alone Mode Single Conversion/
Single Read
Continuous Conversion, Single Read
A variety of applications may call for the A/D to be read after
several conversions. In process control systems, this is often the
case since a reading from a sensor may only need to be updated
every few conversions. Figure 11 shows the timing relationships.
Once again, CE and CS should be tied together. Conversion
will begin when the R/W signal is brought low. The device will
convert repeatedly as indicated by the status line. A final conversion will take place once the R/W line has been brought high.
The rising edge of R/W must occur while STATUS is high. R/W
should not return high while STATUS is low since the circuit is
in a reset state prior to the next conversion. Since the rising
edge of R/W must occur while STATUS is high, R/W’s length
must be a minimum of 10.25 µs (tC + tTD). Data becomes valid
upon completion of the conversion and will remain so until the
CE and CS lines are brought high indicating the end of the read
cycle or R/W goes low initiating a new series of conversions.
Figure 9. Read Cycle Timing
Figure 11. Stand-Alone Mode Continuous Conversion/
Single Read
–8–
REV. A

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Owner`s Manual Ver. 1.1 / January 2016 © Mytek 2016