Thumb Instruction Set Quick Reference Card

Transkrypt

Rotate right
Arithmetic shift right
Logical shift right
Shift/Rotate
Logical shift left
Logical
AND
EOR
OR
Bit clear
Move NOT
Test bits
Immediate
with carry
Negate
Multiply
Compare
Lo and Lo
Lo and Hi
Hi and Lo
Hi and Hi
Negative
Immediate
with carry
Subtract
Arithmetic
Add
Lo and Lo
Hi to Lo
Lo to Hi
Hi to Hi
Immediate
Value to SP
ALU
LSL
LSL
LSR
LSR
ASR
ASR
ROR
Rd,
Rd,
Rd,
Rd,
Rd,
Rd,
Rd,
Rd,
Rd,
Rd,
Rd,
Rd,
Rd,
Rd,
Rd,
Hd,
Hd,
Rd,
Rd,
CMP
CMP
CMP
CMP
CMN
CMP
AND
EOR
ORR
BIC
MVN
TST
Rd,
Rd,
Rd,
Hd,
Hd,
Rd,
SP,
SP,
Rd,
Rd,
Rd,
Rd,
Rd,
Rd,
Rd,
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADC
SUB
SUB
SUB
SBC
NEG
MUL
Rs, #5_Bit_Offset
Rs
Rs, #5_Bit_Offset
Rs
Rs, #5_Bit_Offset
Rs
Rs
Rs
Rs
Rs
Rs
Rs
Rs
Rs
Hs
Rs
Hs
Rs
#8_Bit_Value
Rs, #3_Bit_Value
Rs, Rn
Hs
Rs
Hs
#8_Bit_Value
#Imm
#-Imm
Rs
Rs, Rn
Rs, #3_Bit_Value
#8_Bit_Value
Rs
Rs
Rs
#8_Bit_Value
Hs
Rs
Hs
MOV
MOV
MOV
MOV
Immediate
Hi to Lo
Lo to Hi
Hi to Hi
Move
Rd,
Rd,
Hd,
Hd,
Assembler
Operation
Thumb Instruction Set
Quick Reference Card
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Hi
regs
Lo
regs
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✓
Rd:= Rs << #5_Bit_Offset
Rd:= Rd << Rs
Rd:= Rs >> #5_Bit_Offset
Rd:= Rd >> Rs
Rd:= Rs ASR #5_Bit_Offset
Rd:= Rd ASR Rs
Rd:= Rd ROR Rs
Rd:= Rd AND Rs
Rd:= Rd EOR Rs
Rd:= Rd OR Rs
Rd:= Rd AND NOT Rs
Rd:= NOT Rs
CPSR flags:= Rd AND Rs
CPSR flags:= Rd - Rs
CPSR flags:= Rd - Hs
CPSR flags:= Hd - Rs
CPSR flags:= Hd - Hs
CPSR flags:= Rd + Rs
CPSR flags:= Rd - #8_Bit_Value
Rd:= Rs + #3_Bit_Value
Rd:= Rn + Rs
Rd:= Rd + Hs
Hd:= Hd + Rs
Hd:= Hd + Hs
Rd:= Rd + #8_Bit_Value
SP:= SP + #Imm
SP:= SP + #-Imm
Rd:= Rd +Rs + C-bit
Rd:= Rs - Rn
Rd:= Rs - #3_Bit_Value
Rd:= Rd - #8_Bit_Value
Rd:= Rd - Rs - NOT C-bit
Rd:= -Rs
Rd:= Rd * Rs
Cond Action
codes
Rd:= #8_Bit_Value
✓
Rd:= Hs
Hd:= Rs
Hd:= Hs
5-bit immediate value
Set cond codes on Rd AND Rs
Set cond codes on Rd + Rs
Set cond codes on Rd - Rs
Notes
Load
Branch
Operation
ADD Rd, PC, #Imm
ADD Rd, SP, #Imm
Address
using PC
using SP
LDMIA Rb!, { Rlist }
LDR Rd, [SP, #Imm]
SP-relative
LDRB Rd, [Rb, #Imm]
LDR Rd, [Rb, #Imm]
LDRH Rd, [Rb, #Imm]
BX Rs
BX Hs
BLE label
LDR Rd, [Rb, Ro]
LDRH Rd, [Rb, Ro]
LDRSH Rd, [Rb, Ro]
LDRB Rd, [Rb, Ro]
LDRSB Rd, [Rb, Ro]
LDR Rd, [PC, #Imm]
Multiple
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✓
Rd:= [Rb + #Imm]
Rd:= [Rb + #Imm]
9-bit two’s complement address,
halfword aligned (label>>1)
Equal
Not equal
Unsigned higher or same
Unsigned lower
Negative
Positive or zero
Overflow
No overflow
Unsigned higher
Unsigned lower or same
Greater or equal
Notes
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Rd:= [SP + #Imm]
Rd:= [PC + #Imm]
Rd:= [SP + #Imm]
Rd:= [Rb + Ro]
Rd:= [Rb + Ro]
Rd:= [Rb + Ro]
Rd:= [Rb + Ro]
Rd:= [Rb + Ro]
Rd:= [PC + #Imm]
Rd:= [Rb + #Imm]
10-bit unsigned immediate offset
(word-aligned). PC bit 1 read as 0.
(word-aligned)
Loads list of registers, starting at base
address in Rb. Writes back new address.
Loads bits 0-15 and sets bits 16-31 to 0
Loads bits 0-15 and sets bits 16-31 to bit 15
Loads bits 0-7 and sets bits 8-31 to bit 7
(word-aligned). PC bit 1 read as 0.
(word-aligned)
7-bit immediate offset
8-bit immediate offset.
Loads bit 0-7 and sets bits 8-31 to 0
Toggles between ARM and Thumb state
12-bit two’s complement address, word
aligned (label <<1)
label is 23-bit two’s complement halfword
offset, split into two 11-bit halves (ignoring
bit 0). Encoded as 2 Thumb instructions.
Greater than
✓
✕
Cond Action
codes
BGT label
with register offset
word
halfword
signed halfword
byte
signed byte
PC-relative
byte
Optional state change
to Lo
to Hi
with immediate offset
word
halfword
Hi
regs
Less than
BL label
Lo
regs
BLT label
long branch with link
label
label
label
label
label
label
label
label
label
label
label
B label
BEQ
BNE
BCS
BCC
BMI
BPL
BVS
BVC
BHI
BLS
BGE
Assembler
if Z set
if Z clear
if C set
if C clear
if N set
if N clear
if V set
if V clear
if C set and Z clear
if C clear and Z set
if N set and V set, or
if N clear and V clear
if N set and V clear, or
if N clear and V set
if Z clear, and N or V set, or
if Z clear, and N or V clear
if Z set,or
N set and V clear, or
N clear and V set
unconditional
Conditional
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✓
STMIA Rb!, { Rlist }
Multiple
Telephone:
Facsimile:
Email:
Telephone:
Facsimile:
Email:
+49 89 608 75545
+49 98 608 75599
[email protected]
Advanced RISC Machines Limited
Otto-Hahn Str. 13b
85521 Ottobrun-Riemerling
Munich
Germany
Advanced RISC Machines Limited
Fulbourn Road
Cherry Hinton
Cambridge CB1 4JN
England
+44 1223 400400
+44 1223 400410
[email protected]
GERMANY
ENGLAND
Telephone:
Facsimile:
Email:
+81 44 850 1301
+81 44 850 1308
[email protected]
Advanced RISC Machines K.K.
KSP West Bldg, 3F 300D, 3-2-1 Sakado
Takatsu-ku, Kawasaki-shi
Kanagawa, 213
Japan
JAPAN
This reference card is intended only to assist the reader in the use of the product. ARM Ltd
shall not be liable for any loss or damage arising from the use of any information in this
reference card, or any error or omission in such information, or any incorrect use of the product.
By
BJH
BJH
BJH
Change
Beta draft
First Release
Second Release
Telephone:
Facsimile:
Email:
+1 408 399 5199
+1 408 399 8854
[email protected]
http://www.ar m.com
Full descending stack
Full descending stack
Pre-indexed word store
Stores bits 0-15
Pre-indexed byte store
(word-aligned)
Stores list of registers, starting at base
address in Rb. Writes back new address.
ARM USA
Suite 5, 985 University Avenue
Los Gatos
California 95030
USA
USA
Date
April 1995
June 1995
Sept 1996
Change Log
Issue
Beta
A
B
ARM QRC 0001B
Neither the whole nor any part of the information contained in, or the product described in,
this reference card may be adapted or reproduced in any material form except with the prior
written permission of the copyright holder.
[Rb + Ro]:= Rd
[Rb + Ro]:= Halfword value from Rd
[Rb + Ro]:= Byte value from Rd
[SP + #Imm]:= Rd
Document Number
The product described in this reference card is subject to continuous developments and
improvements. All particulars of the product and its use contained in this reference card are
given by ARM in good faith. However, all warranties implied or expressed, including but not
limited to implied warranties or merchantability, or fitness for purpose, are excluded.
Notes
[Rb + #Imm]:= Rd
[Rb + #Imm]:= Halfword value from Rd 8-bit immediate offset. Stores bits 0-15.
[Rb + #Imm]:= Byte value from Rd
Cond Action
codes
ARM and the ARM Powered logo are trademarks of Advanced RISC Machines Ltd.
SWI #8_Bit_Value
PUSH { Rlist }
PUSH { Rlist, LR}
POP { Rlist}
POP { Rlist, PC }
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STR Rd, [Rb, Ro]
STRH Rd, [Rb, Ro]
STRB Rd, [Rb, Ro]
STR Rd, [SP, #Imm]
Push registers onto stack
Push LR and registers onto stack
Pop registers from stack
Pop registers and PC from stack
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Hi
regs
STR Rd, [Rb, #Imm]
STRH Rd, [Rb, #Imm]
STRB Rd, [Rb, #Imm]
Lo
regs
with immediate offset
word
halfword
byte
with register offset
word
halfword
byte
SP-relative
Assembler
Proprietary Notice
Software
Interrupt
Push/
Pop
Store
Operation

Thumb Instruction Set Quick Reference Card

Transkrypt

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