Splitter

CMS
RPC Muon Trigger
RPC Muon Trigger
Splitter
presented by Maciek Kudla
CMS Electronics Week
CERN
May 13, 2002
CMS Electronics Week - May 13, 2002
Ignacy Maciek Kudla, Warsaw University
CMS
Responsabilities
Link System
Link Boards, Link Crates
- Helsinki, Seul
Splitter Boards, Splitter Crate
- Seul
Trigger, Readout
Trigger Boards, Readout Boards,
Sorter Boards*, Crates
CMS Electronics Week - May 13, 2002
- Warsaw, Bari*
Ignacy Maciek Kudla, Warsaw University
CMS
General remarks
- all detector data (~200 kbits @40 MHz) are transmitted to USC
(compressing/decompressing Link System is used)
- synchronisation and diagnostic is performed (VHDL code in FPGA) after
each interboard transmission (histograms, counters, test triggers)
- only one ASIC forseen - Pattern Comparator (PAC), all other functions
are realized using FPGA (if possible Altera ACEX or Xilinx Spartan),
Stratix emerges as an possible solution for PAC
- all detector data are available for DAQ and are concentrated into
3 SLink connections
CMS Electronics Week - May 13, 2002
Ignacy Maciek Kudla, Warsaw University
CMS
General layout
Detector
Detector
Periphery
Counting Room
Splitter Crate
FEB
LINK BOARD (Slave)
FEC
SPLITTER BOARD
LMUX
LMUX
Tx
electrical
optical
1576
(120 boxes)
Splitter
electrical
SORTER BOARD
(on Backplane)
GB & SORTER BOARD
SORTER
GB
&
SORTER
LMUX
Rx
Sorter Crate
PAC
Splitter
LINK BOARD (Master)
FEC
TRIGGER BOARD
LMUX
Rx
FEB
Trigger Crate
SORTER
SORTER
Diagnostics
CMS Electronics Week - May 13, 2002
3 to
Global
1 Muon
Trigger
SORTER
PAC
204
12
~204
SORTER BOARD
(on Backplane)
SORTER
SORTER
12
data
control (DCS)
TTc Rx
SORTER
SORTER
READOUT
MASTER
BOARD
EVENT
BUILDER
SORTER
READOUT
CONCENTRATOR
BOARD
EVENT
CONCENT
electrical
to
3 DAQ
3 Slinks
electrical
Ignacy Maciek Kudla, Warsaw University
1. 12 splitter crates (SC) are needed. One SC deal with
60+46=106 optical inputs and 206 elictical outputs.
2. SC contains the number of the Splitter Boards (SB).
3. Problem: How to split signals from one SC to the other?
In most cases one optical link goes to two locations.
Seems that optical splitting at this level could be the most
economical solution.
CMS
Splitter Board and Splitter Crate
Splitter Crate
Receives the data dovoted to one Trigger Crate from Link System
and distributes them to the Trigger Boards (up to 3 different boards)
Splitter Board
Receives optical signals and converts them to the electrical ones
(up to 10 inputs and 16 outputs)
Status
- connection table established for wedge architecture
- preliminary Splitter Board - Trigger Board interface established
- prototype Splitter Board in production
CMS Electronics Week - May 13, 2002
Ignacy Maciek Kudla, Warsaw University
CMS
Splitter
Splitter (Korea) - test board
sdp
sdm
preamp
Internal
limiting
amp
Limiting
Amp.
Clock
Recovery
clkp
clkm
(160MHz)
sdp
sdm
pdp
pdm
Deserialiser
clkp
clkm
Il Park - Seul Nat. Univ.
Seong Hong - Korea Univ.
clock
(160MHz)
data
sync (data marker)
clock (80MHz)
LVDS
Driver
LVDS
Driver
Connector
data
sync (data marker)
clock (80MHz)
Connector
FPGA
Intermediate solution to develop Link Board - Trigger Board interface - several boards
in preparation in Seul
CMS Electronics Week - May 13, 2002
Ignacy Maciek Kudla, Warsaw University
CMS
LB - Splitter - TB tests
LB - Splitter - TB tests
VME
LBrf1
TB 1
VME
Interface
TB 2
Slave
1
Lmux
Internal bus
Control
I2C bus
Slave
2
Synchro
Clock
TTCrx
GOL
FEB 1
FEB 2
FEB 4
Splitter
1
FEB 3
FEB 5
TB
Memory
Buffer
256kx16
Clock
Driver
TTC
Test Board
FEB 6
Delay
CLK_CON
BS ch1
Clock
Driver
BS ch2
Delay
VME
LBrf2
TB 1
TB 2
LVDS
SP_CON1
14
LVDS
SP_CON2
Synch
Diag
Readout
20
20
32
LDEMUX
4
16
Slave
1
Lmux
SP_CON1
LVDS
SP_CON2
Internal bus
Control I2C bus
Synch
Diag
Readout
28
LDEMUX
3
12
4
12
4
32
LVDS
VME
Interface
PC
Unix
16
14
16
VME
Interface
(EPROM)
VME Conn
Clock
Driver
BS ch2
BS ch1
Splitter
2
VME
Interface
(Ext.)
JTAG
Controller
Ethernet
PAC 1
16
PAC 2
28
BS ch2
PAC 3
Slave
2
Synchro
LVDS
SP_CON1
LVDS
SP_CON2
GB
Sorter
Diag
20
Synch
Diag
Readout
LDEMUX
2
20
Synch
Diag
Readout
LDEMUX
1
32
Trigger
PAC 4
Clock
TTCrx
GOL
LVDS
SP_CON1
LVDS
SP_CON2
FEB 1
FEB 2
PAC 5
32
FEB 3
BS ch1
Read_Conn
FEB 4
FEB 5
CMS Electronics Week - May 13, 2002
Diag
FEB 6
Ignacy Maciek Kudla, Warsaw University