Lista publikacji - Wydział Informatyki - PB

Białystok, 01.07.2016 r.
mgr inż. Maciej Kopczyński
Katedra Systemów Informacyjnych i Sieci Komputerowych
Wydział Informatyki
Politechnika Białostocka
Lista publikacji:
1. M. Kopczyński, J. Stepaniuk: Rough set methods and hardware implementations, Zeszyty
Naukowe Politechniki Białostockiej. Informatyka Zeszyt 8, 2011, pp. 5–18.
2. M. Kopczyński, J. Stepaniuk: Hardware Implementations of Rough Set Methods in
Programmable Logic Devices, Rough Sets and Intelligent Systems - Professor Zdzisław
Pawlak in Memoriam, eds. Andrzej Skowron, Zbigniew Suraj, Intelligent Systems
Reference Library 43, Heidelberg, Springer, 2012, pp. 309–321.
3. J. Stepaniuk, M. Kopczyński, T. Grześ: The First Step Toward Processor for Rough Set
Methods, Fundamenta Informaticae Vol. 127, 2013, pp. 429–443.
4. T. Grześ, M. Kopczyński, J. Stepaniuk: FPGA in rough set based core and reduct
computation, Lecture Notes in Computer Science Vol. 8171: Lecture Notes in Artificial
Intelligence, Rough sets and knowledge technology: 8th International Conference:
RSKT’2013, eds. Pawan Lingras, Marcin Wolski, Chris Cornelis, Sushmita Mitra, Piotr
Wasilewski, Berlin, Springer-Verlag, 2013, pp. 263–270.
5. M. Kopczyński, T. Grześ, J. Stepaniuk: FPGA in Rough-Granular Computing : Reduct
Generation, WI 2014 : The 2014 IEEE/WCI/ACM International Joint Conferences on Web
Intelligence Vol 2, eds. Andrzej Skowron, Lipika Dey, Adam Krasuski, Yuefeng Li, IEEE,
Warsaw, 2014, pp. 364-370.
6.
M. Kopczyński, T. Grześ, J. Stepaniuk: Generating core in rough set theory : Design and
implementation on FPGA, Lecture Notes in Computer Science Vol. 8537: Lecture Notes in
Artificial Intelligence, Rough sets and intelligent systems paradigms: Second International
Conference: RSEISP’2014: Held as Part of JRS 2014, eds. Marzena Kryszkiewicz, Chris
Cornelis, Dave Ciucci, Jesus Medina-Moreno, Hiroshi Motoda, Zbigniew W. Raś, SpringerVerlag, Berlin, 2014, pp. 209-206.
7. M. Kopczyński, J. Stepaniuk, T. Grześ: Realizacja algorytmu sekwencyjnego wyznaczania
macierzy rozróżnialności zbioru przybliżonych w układzie FPGA, Pomiary, Automatyka,
Kontrola Vol. 60, pp. 321-324.
8. M. Kopczyński, T. Grześ, J. Stepaniuk: Core for Large Datasets : Rough Sets on FPGA,
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Concurrency, Specification & Programming: 24th International Workshop: CS&P 2015 Vol
1, eds. Zbigniew Suraj, Ludwik Czaja, Rzeszów, 2015, pp. 235-246.
9. M. Kopczyński, T. Grześ, J. Stepaniuk: Computation of Cores in Big Datasets: An FPGA
Approach, Lecture Notes in Computer Science Vol. 9436: Lecture Notes in Artificial
Intelligence, Rough Sets and Knowledge Technology: 10th International Conference: RSKT
2015: Held as Part of the International Joint Conference on Rough Sets: IJCRS 2015:
proceedings, eds. Davide Ciucci, Guoyin Wang Sushmita Mitra, Wei-Zhi Wu, Cham,
Springer, 2015, pp. 153-163.
10. M. Kopczyński, T. Grześ, J. Stepaniuk: Maximal Discernibility Discretization of Attributes a FPGA Approach, Machine Intelligence and Big Data in Industry, Studies in Big Data, eds.
Dominik Ryżko, Cham, Springer, 2016, pp. 171-180.
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